Timing analysis for synthesis in microprocessor interface design

Design automation techniques are playing an important role in controlling the complexity of system design. The authors' work is inscribed in the design automation of microprocessor-based systems which necessitates the design of interfaces for system integration. During the interface synthesis it is required to validate the timing of a design yet to be implemented. In this paper they present a novel methodology to timing analysis that can determine tight bounds on interface path delays based on the given timing information. The timing analysis for synthesis problem is formulated as a combinatorial optimization problem using interval arithmetic techniques.<
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