An 8-bit multitask micropower RISC core

This paper describes a multitask micropower RISC core. A hardware scheduler handles up to four separate tasks in a pseudo-parallel way. Task or context switching is performed at the instruction level and does not need additional instructions. In a 1.5-V low-power 2-/spl mu/m technology the core area is 5-6 mm/sup 2/, depending upon the global routing of the complete ASIC. Measured power consumption is 0.2 /spl mu/A/kHz at 1.5 V with a low-power 8-K word ROM and a 256-byte RAM.<
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