A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-/spl mu/m CMOS

A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-/spl mu/m CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm/sup 2/ and the core of the parallel ADC array occupies an area of 2.7/spl times/3.3 mm/sup 2/. The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively.<
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