Specification, design and implementation of a digital binary image processing ASIC

A novel binary image processing ASIC is described. The architecture of this ASIC is particularly well suited to high-speed nonlinear functions. The ASICs function is to filter an incoming data stream which represents an image of width 512 pixels. The data is initially thresholded to a binary data stream. This resulting data stream is then fed through a series of line delays, to effect a 3 by 3 pixel neighbourhood, or window, scanning across the threshold image. The nine binary pixel values in this neighbourhood are used as an address into an on-chip SRAM, which is used as a look up table (LUT) and memory contents at this address serve as output for the device. For cascading purposes, the window contents and the thresholded image are available as output from the device. This device has applications in image pre-processing and filtering in, for example, the area of machine vision. The user may tune the response of the filter for most image pre-processing tasks. Several ICs can be cascaded together to effect any size or shape of window and various binary filters are implemented by appropriate programming of the SRAM. ASIC design has been completed and the device is currently being fabricated.<
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