A complex adaptive equalizer ASIC

An adaptive equalizer ASIC has been developed with a structure which implements either the FIR filter function or the adaptive weight generator function. The ASIC contains full complex arithmetic, saturation logic, tap leakage logic, complex conjugation, and selectable adaptation loop gain, and is cascadable without external logic. It contains 4 taps, cascadable to 8 T-spaced or 16 T/2-spaced taps, with each tap having 4 8*8 bit multipliers. The ASIC supports a 10 MHz throughput rate.<
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