An ETL gate array implementation of a 2.5 Gb/s, 48-bit wide, channel programmable demultiplexer for fiber optic data transmission

Describes unique circuit and logic design techniques in the implementation of a 48-channel programmable demultiplexer using a mature, high-yielding, bipolar ECL gate array for data transmission at 2.5 Gb/s. The new high-frequency macros and the unique design of the timing control circuitry enable a mature process technology to be used to more than double the operating rate of the technology compared to standard methods.<
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