Tutorial on design for testability

Testability must be incorporated in all phases of an ASIC design, including wafer level, chip level, I/O level, and board/system level. Level-sensitive scan design (LSSD) is a design technique that uses latches and flip-flops that are level sensitive as opposed to edge triggered. The basic approach of LSSD is to make a sequential network appear like combinatorial logic during testing by logically eliminating feedback loops. LSSD, scan techniques, boundary scan requirements (IEEE 1149.1), and built-in self test (BIST) concepts for memories are described.<
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