A 1.2 mu m CMOS differential I/O system capable of 400 Mbps transmission rates

High-bandwidth processor-to-processor connections, like the IEEE Std. 1596 scalable coherent interface (SCI), are being proposed as functional replacements for computer-system buses. To be cost-effective, it is important to drive the SCI links directly from CMOS VLSI components. To meet this need, a low-power, low-voltage-swing CMOS differential I/O driver/receiver system has been developed and is described. Measured results demonstrate 400-Mbps switching speeds using 1.2- mu m CMOS technology.<
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