A 5 volt 0.5 mu m mixed BiCMOS/CMOS channelless gate array

A 0.5- mu m BiCMOS/CMOS gate array that incorporates a new basic cell topology with an uneven mix of MOS and bipolar devices is described. This approach is aimed at maximizing the utilization of a BiCMOS gate array by enabling three kinds of macros to be implemented without any silicon penalty: low-power CMOS, high-drive CMOS, and BiCMOS. Fabricated with 0.5- mu m BiCMOS technology, the 5-V gate array features input and output buffers that can support TTL and ECL logic levels, as well as pseudo-ECL levels.<
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