High-speed low-power Darlington ECL circuit

Presents an ECL circuit with a Darlington configured dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array application. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8- mu m double-poly self-aligned bipolar technology at a power consumption of 1 mW/gate, the circuit offers 28% improvement in the loaded (FI/FO=3, C/sub L/=0.3 pF) delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed.<
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