A reconfigurable superchip for VLSI processing arrays

A reconfigurable sparse matrix superchip (SMS) for VLSI processing arrays is presented. The superchip architecture, its reconfiguration, and routing strategies are discussed. The application of the SMS for basic signal processing computations like matrix-vector and matrix-matrix multiplications is illustrated. The SMS implementations promise to be more economical and faster than the original systolic arrays or the more recent engaged processor systolic array; for a matrix-vector multiplication, the SMS implementation is twice as fast and for matrix-matrix multiplication it is three times faster than systolic array implementations. The SMS implementations also require less processing elements.<
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