A constant-geometry semisystolic architecture for the fast Hartley transform

A parallel architecture is presented for the calculation of the fast Hartley transform (FHT) radix 2 which is adequate for its implementation in VLSI technology. A constant geometry (frequency decimation) algorithm for computing the FHT has been developed. The circuit proposed is characterized by its modular design and its interconnection regularity. It can be considered as semisystolic. It permits the computation of arbitrarily sized FHTs as a consequence of data recirculation over the processing units in all the stages of the transform. Each calculation stage requires N/4Q cycles, where N and Q are the length of the input real sequence and the number of processors respectively. The system calculates the FHT in log/sub 2/ N stages; therefore, the total calculation time is (N log/sub 2/ N)/4Q cycles.<
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