A proposed standard test bus and boundary scan architecture

The author describes the test interface and boundary scan architecture proposed in the Joint Test Action Group (JTAG) 2.0 specification. The test access port described in the JTAG specification meets the requirements for a standard serial test interface. The architecture is flexible enough to support test structures ranging from boundary scan to the sophisticated maintenance and support structures required in the high end military and commercial arena of the electronics industry. Features discussed include the test access port, the instruction register, and the data register.<
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