Width minimization of field encoded outputs

A new technique for minimizing the width of programmable logic devices (PLDs) is introduced. A weighting technique is introduced, which assigns a weight to each micro-order equal to the size of the largest reserved class containing it. The micro-orders with the largest weights are tripped from each class to form a stripped set. The stripped microorders are tested for compatibility, and a new set of compatibility classes is formed from the stripped microorders, and the microorders in the reserved classes only. The average accuracy, ((PLD width obtained)/(minimum PLD width)), of the new technique was 99.85%.<
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