Rapid migration to VLSI

The use of design tools to create a 115,000-gate equivalent array within three generations is described. The first generation consisted of a 7800-gate equivalent array containing the glue logic for a dual redundant serial bus and was housed in a 120-pin ceramic pin grid array (PGA). CAE work stations are used for the creation of the design, and vendor-specific tools are used for final simulations. The second generation fully embedded the PGA into the array to support an Intel 80960 CPU. The second-generation ASIC was housed in a 256-pin quad flat pack (QFP) and was created on work stations utilizing vendor-specific tools. The third generation, a 115,000-gate equipment array, added a second PGA, three universal asynchronous receiver transmitters (UARTs), and two synchronous data-link control serial ports permitting the creation of a stand-alone computer I/O card in a single assembly.<
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