A numerically stable pipeline net VLSI architecture for the isomorphic Hopfield model

An isomorphic model is introduced to reduce the complexity of the Hopfield model's digital implementations. To ensure numerical solution with stability and a prescribed accuracy, a mixed-type integration algorithm based on combining a single-step Runge-Kutta method and a multistep predictor-corrector method is applied to the digital simulation of the isomorphic model. A reconfigurable pipeline net VLSI architecture is proposed to implement the mixed-type integration algorithm. The architecture is composed of four processors, a programmable 12*30 routing network, and a 6*n shifter array, which are assigned to deal with the main operations of the integration algorithm, data routing, and synchronization, respectively.<
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