Don't care set specifications in combinational and synchronous logic circuits

A unified framework for the specification and computation of don't care conditions for combinational and synchronous multiple-level digital circuits is presented. Circuits are characterized in terms of graphs, logic functions and don't care conditions induced by the external and internal interconnections. The replacement of a gate in a synchronous logic network is modeled by a perturbation of the corresponding logic function, and it is shown that the don't care conditions for the gate optimization represent the bound on this perturbation. Algorithms to compute such don't care conditions in both the combinational and synchronous case are presented. The implementation of the algorithms and the experimental results are discussed.<
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