A 10-b 300-MHz interpolated-parallel A/D converter

A monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz is described. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V/sub be/ matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within +or-0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of -59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0-mm*4.2-mm chip integrating 36 K elements, which consumes 4.0 W using a 1.0- mu m-rule, 25-GHz f/sub t/, double-polysilicon self-aligned bipolar technology.<
>