Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits

A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell's critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32*32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method.<
>