Boundary scan design for a memory controller

A boundary-scan design that fully conforms to the IEEE 1149.1 standard has been incorporated in MEMC2, a complete memory and system controller for ARM-based systems. MEMC2 provides a two level memory management system: Level 1 Page Tables are stored on-chip for improved access speed while the larger Level 2 Tables are stored in main memory. An on-chip 64-entry Translation Lookaside Buffer of Level 2 Page Tables further improves performance by caching most recently used translations. The chip can control a large DRAM memory system; it also provides support for static RAM and ROM and provides a video interface and seven on-chip DMA channels. This device has recently been fabricated by VLSI Technology in their 1.0 mu m double-level metal CMOS process and it is fully functional.<
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