Time division multiplexing with orthogonal RAMs

A technique for time-division multiplexing is described. Multiplexing and demultiplexing is achieved with a type of memory array in which reading is performed orthogonally to writing. The orthogonal memory provides storage and serial-to-parallel (plus parallel-to-serial) conversion in a regular and compact structure. This results in reduced chip area, reduced power dissipation, and an increased speed-density product, making the scheme ideal for VLSI implementation. The orthogonal RAM has been implemented in 1.2- mu m CMOS, and basic operation has been validated.<
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