A 2.5 Gbit/s GaAs clock and data regenerator IC

Monolithic integration of a clock and data regenerator operating at 2.5 Gbit/s has been achieved using analog design techniques applied to a GaAs heterojunction FET (HFET) process. The GaAs IC, which performs clock and data regeneration functions for high-speed fiber-optic transmission systems, is presented. This IC, in conjunction with a companion Si bipolar circuit, can regenerate pseudorandom NRZ data error-free at rates exceeding 2.5 Gbit/s with a sensitivity of 25 mV. The recovered clock has less than 7-ps RMS edge jitter. The chip draws 250 mA from a single 5.2 V ECL-compatible power supply.<
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