A WSI rapid prototyping architecture

Describes a generalized architecture, the WSI architecture for rapid prototyping (WARP), which attempts to map a large class of algorithms with only two types of processing cells. These are (a) the universal multiply-subtract-add cell (UMSA), and (b) the universal nonlinear cell (UNL). Using these cells, the authors have mapped a radix-8 FFT (fast Fourier transform) algorithm to a wafer architecture as well as the L-U decomposition onto the prototyping architecture. The authors report on reconfiguration using pooled redundancy, a compromise between completely global redundancy and completely local redundancy. They also discuss a harvesting model which quickly leads to an estimate of wafer yield. Using this tool the designer can make tradeoffs between the provisioning of needed functional cells and spares, and the desired yield.<
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