Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques

This paper proposes a bus architecture which improves the performance and/or power dissipation of online buses. The proposed architecture reduces the delay on alternate lines by lowering the threshold voltage of its devices. Furthermore, the shifting of the signal switching on adjacent lines reduces the worst case coupling capacitance. Two implementations of this bus architecture are proposed, the alternate-V
_t
and the alternate forward body biased schemes, and are compared to a conventional bus scheme. For a flop distance of 1800 mum, the proposed schemes use the gained delay slack to reduce the total device width, and thus reducing the energy dissipation by 31.2%. For a 500-ps cycle time, the proposed bus schemes increase the maximum distance between flip-flops by 33%