An OPLL-DDS based frequency synthesizer for DCS-1800 receiver

A frequency synthesizer combining offset phase-locked loop (OPLL) and direct-digital synthesis (DDS) is presented in this paper. DDS is for channel selection as it inherits fast settling and fine resolution characteristics. OPLL structure helps to lower the DDS operation speed thus reduce the power dissipation. Compared with the conventional PLL, this structure relieves the tradeoff between loop bandwidth and settling time requirement. System analysis shows that this structure can meet the stringent requirement of DCS1800. This structure is designed with a 0.18 mum CMOS process. Excluding of DDS, the synthesizer core dissipates 9.5mW from a 1.8V supply