An adaptive FPGA architecture with process variation compensation and reduced leakage

Process induced threshold voltage variations bring about fluctuations in circuit delay that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensates for these fluctuations. The architecture includes an additional characterizer circuit that classifies logic and routing blocks on each die according to their performance. Base on this classification, the architecture adaptively body-biases these resources by either speeding up the slow blocks or by slowing down the leaky ones. This procedure mitigates the effect of the variations and provides a better yield. We further diminish leakage by slowing down areas of the FPGA that have a positive slack. Overall, this architecture minimizes the timing variance of within-die and die-to-die V/sub th/ variations by up to 3.45/spl times/ and reduces leakage power in the non-critical areas of the FPGA by 3/spl times/ with no effect on frequency.