Self-heating Eeffects in SOI NLDEMOS Power Devices

Self-heating is evaluated in high-voltage devices from a 0.13 mum thin-film SOI CMOS technology. Our measurement procedure is described. The influence of different parameters such as layout variations is finally investigated, and main results are shown here. A strong linear correlation between the thermal resistance and the reverse of the active surface is demonstrated. Besides, a moderate impact of the metallization is observed