Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities

This paper proposes a simple and accurate expression for inverter effective drive current for nanoscale Si and carbon nanotube FET (CNFET) performance benchmarking. The choice of I/sub eff/=(I/sub NL/+I/sub NM/+I/sub NH/-I/sub P/)/3, where I/sub NL/=I/sub DS(N-FET)/ (V/sub GS/=0.5V/sub DD/, V/sub DS/=V/sub DD/), I/sub NM/=I/sub DS(N-FET)/(V/sub GS/=0.75V/sub DD/, V/sub DS/=0.75V/sub DD/), I/sub NH/=I/sub DS(N-FET)/ (V/sub GS/=V/sub DD/, V/sub DS/=0.5V/sub DD/), and I/sub P/=I/sub SD(P-FET)/ (V/sub SG/=0.25V/sub DD/, V/sub SD/=0.25V/sub DD/), includes the effects of both the nFET and the pFET of an inverter and accurately captures the inverter delay performance over many CMOS technology nodes and in the presence of device nonidealities. The proposed metric indicates that the performance enhancement of CNFETs over Si MOSFETs is not as large as that predicted by I/sub Dsat/ in a circuit environment because of the nonideal I-V characteristics.