Digital design of DS-CDMA transmitter using VHDL and FPGA

This paper describes the direct sequence code division multiple access (DS-CDMA) wireless transmitter design using field programmable gate array (FPGA), which has been adopted in many wireless access technologies. Four separate blocks have been designed using digital approach to form the transmitter circuit diagram using the oscillator, the PN-code generator, the parity check, and the BPSK modulator. The Synopsys software has been used for the design synthesis and simulation; the very high speed integrated circuit hardware description language (VHDL) program was used for coding and FPGA for compiling and downloading the simulation. The DS-CDMA wireless transmitter was designed to transmit with data rates up to 2 Mbps. The transmitted signals were carried with a 40 MHz carrier frequency.