Back gate effects in thick film SOI CMOS devices

A 30-V bulk p-well CMOS process has been implemented on nominally 5- mu m bonded SOI (silicon-on-insulator) wafers using trench isolation to produce fully dielectrically isolated devices. By a suitable choice of doping levels, the SOI version of the process can be made to have the same electrical parameters as the bulk version. However, back gate controlled leakage of the PMOS devices has been observed. Several solutions to this problem are possible, including modification of the silicon layer doping, modification of the silicon layer thickness, and controlling the potential of the handle wafer.<
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