A parallel analog CCD/CMOS neural network IC

A mixed analog/digital neural network chip is presented that uses standard 2- mu m CCD/CMOS fabrication. The device incorporates a matrix of charge injection device elements which hold a matrix of charge encoding the synapse strengths. A vector-matrix multiplier with simple charge-domain multiply-accumulate units has been implemented. The device computes the product of a binary vector and an analog matrix of charge, providing an analog output vector. At a clock rate of 1 MHz, the fabricated device computes 64 million binary/analog multiply accumulates per second in a very small area. The matrix refresh time is small compared to the refresh period.<
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