Linearity optimization of a high power Doherty amplifier based on post-distortion compensation

The linearity of a 30-W high-power Doherty amplifier is optimized using post-distortion compensation. A balanced high-power Doherty amplifier using two push-pull laterally-diffused metal-oxide semiconductor (LDMOS) field-effect transistors (FETs) is linearized by optimum adjustment of the peaking compensation line, shunt capacitors, and gate biases. The measured results of an optimized Doherty amplifier for a four-carrier wideband code division multiple access (W-CDMA) signal, achieved -43 dBc adjacent channel leakage ratio (ACLR) at a /spl plusmn/5 MHz offset frequency. This is an ACLR improvement of 12.2dB and 6.5dB in comparison to the Doherty amplifier before optimization and a ClassAB amplifier, respectively.