Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology

This paper examines the design and implementation of a fourth-order low-pass delta-sigma modulator using a systematic top-down design methodology. Special effort has been made to reduce the power consumption of the modulator through careful system-level modeling and synthesis of circuit specifications. Tradeoffs between circuit building block specifications, optimization time and computing resources are derived. This system-level modeling was tested through the successful implementation of a switched-capacitor delta-sigma analog-to-digital converter integrated circuit (IC) with an output rate slightly exceeding 2 MS/s, in a 1.8-V 0.18-/spl mu/m, single-polysilicon six-metal standard CMOS process. When sampled at 50 MHz, experimental results reveal that the IC achieves 77.6-dB dynamic range. The prototype consumes 18.8 mW of power, making it one of the lowest power dissipations in switched-capacitor implementations, and for applications where output rates exceed 2 MS/s. When compared to other state-of-the-art switched-capacitor modulators using a widely adopted figure of merit, the modulator dissipates less power and offers superior overall performance.