On /spl Delta//spl Sigma/ fractional-N frequency synthesizers

/spl Delta//spl Sigma/ fractional-N frequency synthesis achieves low phase noise performance while relaxing the phase-locked loop (PLL) design constraints and reduces the desired channel spacing. This paper reviews the recent advanced techniques on the implementation of fractional-N frequency synthesizers and discusses their advantages and disadvantages. It also addresses the design options and the associated trade-offs.