A pipeline processor for mixed-size FFTs

A method for performing fast Fourier transforms (FFTs) of various sizes simultaneously in one pipeline processor is described. The processor consists of several stages of butterfly computational elements alternated with delay-switch-delay (DSD) modules that reorder the data between the butterfly stages. By properly ordering the input data to the pipeline and the butterfly twiddle factors, the DSD operations in the pipeline can be performed in any desired sequence, enhancing fault tolerance in case of a partial failure in one or more of the DSD modules. If one of the DSDs is no longer capable of operating in its prescribed mode, it is assigned a different operating mode. All the required changes are performed by software control. It is shown that any mixture of FFTs whose sizes are powers of the pipeline's radix can be performed. For FFTs of radix 2, radix 4, and mixed 2 and 4, the principles of operation are explained and examples of timing diagrams are given.<
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