Optimization of breakdown voltage and on-resistance of VDMOS transistors

The combined effect of the spacing between adjacent drain junctions, epilayer thickness, and resistivity in VDMOS transistors on both its breakdown voltage and
R_{on} \cdot A
product is investigated. It is shown that an increase in the breakdown voltage results as the junctions spacing is reduced. That gives a significant difference in the
R_{on} \cdot A
product when compared with results where this effect is ignored. A design optimization study is carried out to determine the parameters of a VDMOS transistor at 1000-V breakdown.