Stacked transistors CMOS (ST-MOS), an NMOS technology modified to CMOS

This paper describes how standard NMOS technology can be modified to provide CMOS devices [1]. This is done by creating p-channel transistors in an active polysilicon layer. This stacked transistors CMOS (ST-CMOS) technology may be considered as a step towards a three-dimensional (3-D) integration, which is a possible approach for increasing the IC's packing density. All of the steps in the process are standard but one: the laser annealing of processed wafers. A crucial step in this ST-CMOS process is the laser annealing of a multilayer structure: the technique of selective annealing has been developed and optimized.