SOS/CMOS as a high-performance LSI device

To realize a high-performance LSI, the devices used should satisfy the following requirements: 1) high-speed operation, 2) low power consumption, 3) easy designability, and 4) high integration capability. SOS/CMOS has been examined both experimentally and theoretically for these aspects. Ideal CMOS operation with
\tau_{pd} \sim 100
ps with 0.1-pJ energy required to switch an inverter is obtained. 1-GHz operation is confirmed on dynamic 1/16 frequency dividers with 1.0-µm effective channel-length devices. Using the same device, a maximum multiplying time,
\tau_{mul} \sim 25
ns at 5 V with 15-mW average power at 10
⁷
multiplications/s is obtained on a 4 × 4 parallel multiplier. The above result agrees with circuit simulation predictions without including stray capacitance associated with the wiring. The same simulation predicts
\tau_{mul} \sim 60
ns with a maximum power dissipation of 200 mW at 16-MHz operation for a 16 × 16 parallel multiplier. This prediction is also confirmed experimentally. These facts indicate good designability of SOS/CMOS. For larger scale integration capability estimation, power dissipation and wiring delay were examined theoretically for bulk NMOS, bulk CMOS, and SOS/CMOS. The results indicate that for smaller scale integration, bulk NMOS and SOS/CMOS operate faster than bulk CMOS. However, for larger scale integration, SOS/CMOS operates faster than bulk CMOS which, in turn, operates faster than bulk NMOS.