Epitaxial π-ν n-p-n high-voltage power transistors

A new silicon power-transistor structure has been developed which expands the frontiers of power-switching performance and high-voltage power-handling capability. This new structure employs a unique π-ν (nearly intrinsic p- and n-type) epitaxial-layer construction which utilizes "overlay" emitter concepts to achieve improved volt-ampere densities and expanded second-breakdown performance. An n
⁺
-p-π-ν-n
⁺
transistor structure is constructed using alternately grown π and ν, epitaxial high-resistivity layers, p-type base and n
⁺
emitter diffusions are used in the conventional manner to assure punch-through protection. The depletion region for the n
⁺
-p-π-ν-n
⁺
transistor is in the π base and the ν collector, and the maximum electrical field (
E_{\max}
) is at the π-ν interface. The avalanche breakdown V
B
of the device can be controlled by the thickness (
X_{n}, X_{p}
) and the concentration (
N_{A}, N_{D}
) of the π-ν layers. Limiting the thickness of the ν collector region and adjusting the thickness of the π base layer provides a transistor with optimum volt-ampere capability. Various π-ν structures have been fabricated and are evaluated electrically for power switching and for linear applications.