A DC-2.5GHz wide dynamic-range attenuator in 0.13/spl mu/m CMOS technology

A CMOS attenuator with wide dynamic range has been designed and fabricated in a 0.13/spl mu/m CMOS process. The design employs two nonidentical cascaded T-stages that are activated consecutively to improve linearity. The design operates in the frequency band of DC-2.5GHz with 0.9-3.5dB insertion loss and 42dB maximum attenuation in the entire frequency range. Worst case SII is -8.2dB across the frequency band. The design achieves an IIP3 of +20 dBm at mid-attenuation.