Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

Using a novel process flow, we managed to cointegrate several devices on the same wafer; single gate (SG), ground plane (GP), perfectly aligned double gate (DG), misaligned DG and oversized back-gate DG. This paper reports the experimental evaluation of the gate architectures influence on the performance of silicon-on-insulator MOSFETs. DG MOSFETs, with gate lengths down to 40 nm, are experimentally compared to SG and GP MOSFETs. Short-channel effect (SCE) control, static performance and mobility are quantified for each architecture. When compared to SG and GP transistors, the DG transistor shows the best SCE control and performance as predicted by simulations. Gate coupling is demonstrated to be a sensitive and a nondestructive method to evaluate the real on-wafer alignment. Using this method, we report an experimental analysis of gate misalignment influence on DG MOSFETs' performance and SCE. It is found that misalignment primarily affects the subthreshold parameters due to an electrostatic control loss. The DG MOSFET with a slightly oversized back gate (10 nm on each side of the top gate) is a promising solution, if a 10% loss in dynamic performance can be tolerated.