Silicon-oxide interface studies by a photoelectric technique

The growth of oxide layers on silicon is frequently carried out during the fabrication of integrated circuits. This paper describes the results of the study of the oxide layer and the Si-SiO
2
interface in a MOS configuration, by a photoelectric technique. The interface barrier height and the built-in voltage V
MS
in the oxide layer of a MOS structure are measured. The effect of ion migration has been studied by subjecting the structure to bias-heat (BH) treatment. We have constructed the band energy diagram for a p-type 0.001 Ω ċ cm MOS structure, both before and after BH treatment. The photoelectric technique is found to be a convenient tool to study and compare different oxidation processes.