Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility

Summary form only given. The next generation of wireless communication systems will be cognitive to efficiently use the available bandwidth. For a given criterion, these systems will adaptively select the transmission method, protocol and the services which are optimal at any given time. Sophisticated signal processing algorithms of ultra high complexity must be executed to perform this adaptation. To meet conflicting goals such as energy efficiency and flexibility together with cost, time-to-market and reusability constraints a radically different, truly innovative architectural approach is necessary for SoCs applied to wireless communications. These future SoCs can be viewed as heterogeneous multiprocessor systems (MP-SoC). They will contain an increasing number of application specific instruction-set processors (ASIPs) combined with complex memory hierarchies and on-chip communication networks (NoC). The success of the proposed MP-SoC is ultimately linked to the availability of an equally innovative system-level design (SLD) methodology together with the corresponding SLD tool suite. In this presentation, we address this innovative SLD design flow in the context of wireless communications. The focus of this presentation is primarily on one crucial aspect of this process: the spatial mapping of application tasks onto ASIPs.