Efficient functional verification for mixed signal IP

We describe a methodology for verifying the functional operation of a mixed-signal circuit block to be used in a larger integrated circuit. Methodology requirements are outlined, including: compatibility with digital verification at the chip level, compatibility with circuit analysis at the block level, and compatibility with project schedule and resource availability. The methodology is described with examples on a case-study using a 10/100 Ethernet physical layer implementation. Results from the case study show the benefits of applying the methodology to future mixed-signal design projects.