Software architecture of universal hardware modeler

Hardware modeling technology allows complex VLSI devices to be modeled for logic and fault simulation in system-level design verification. The current design environment for digital electronic systems defines the need for a universal hardware modeler (i.e., one that functions with multiple hosts and multiple simulators), as well as for improving overall functionality and performance. The authors describe researched architectural design goals for the LM-1000 universal hardware modeler, along with implementation decisions, tradeoffs and the resultant architecture. The LM-1000 system is currently in production, and performance metrics demonstrate the extent to which project goals were fulfilled.<
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