Design and optimization of CMOS current mode logic dividers

We designed and measured a high-speed CML divider in a 0.18 /spl mu/m CMOS process. The fabricated chip operates at up to 10GHz with power consumption of 8.6mW. From a small-signal equivalent circuit model, we derive an analytical performance model that gives the relationship among maximum operation frequency, gate width and load resistance. We also discuss the design optimization based on the derived performance model.