Microsystems packaging from milli to microscale to nanoscale

So called "packaging", in the past, played two roles: (1) provide I/O connections to the semiconductor devices so the IC is tested and ready for board assembly. This is called IC packaging and (2) integrate components into systems to form end product systems such as cell phones, PDAs, Laptops. This is called systems packaging. Both the above IC and systems packaging are accomplished by interconnections or wiring at the package or board level so far. Packaging is currently at milliscale in manufacturing, microscale in development and nanoscale in research. In future, the role of packaging is more than interconnections. The IC devices themselves began to integrate more and more transistors and functions, leading to what the community have been calling SOC or system-on-chip with multiple systems functions in a single chip. This can be called horizontal or 2D integration of IC blocks toward system-level functionality. The community began to realize, however, that such an approach presents design complexity and fundamental limits for computing, and integration limits for wireless systems, over the long run. This led to 3D packaging approaches, often referred to as SIP or system-in-package. Both these are the latest and most leading-edge technologies pushing the IC integration in two and three dimensions. But they both have one major shortcoming. They depend on CMOS processing and hence are limited by what can achieved with CMOS. The SIP and SOC approaches, while providing major opportunities in both miniaturization and integration for advanced portable and desktop electronic products, are limited by CMOS processes. A new concept called SOP or system-on-package being pioneered by Georgia Tech PRC - where the package, and not the board, is the entire system. SOP addresses the shortcomings of both SOC and SIP in two ways: optimize silicon for what it is good for, and the package for what it is best at, by means of IC/package/system co-design, while doing so, SOP optimizes both for cost, performance, miniaturization and reliability. The package, in this concept, therefore overcomes both computing limitations and integration limitations of SOC and SIP. It does this by having global wiring as well as RF and optical component integration in the package level, and not in the chip. The SOP, therefore, includes embedded digital, RF and optical components and functions built into a highly miniaturized package, module or board for emerging convergent systems of tomorrow. This Moore's Law for systems integration is akin to Moore's Law for ICs pushing component density by a factor of 100 to 10,000 by means of microscale thin film component integration in the short term to nanoscale integration in the long term.