A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications

Design of a high-speed low-to-medium resolution analog-to-digital converter with closed-loop pipeline structure has been investigated. We demonstrate a single-path 600MS/s, 5-bit ADC. It is optimally designed to meet the requirements of a serial-link receiver. For high input-bandwidth, total input-capacitance is only 170fF. At high frequencies, to improve resolution beyond the amplifier-settling limit, the reference voltage of each pipeline-stage is digitally tuned. The chip is fabricated in 0.18 /spl mu/m CMOS technology and consumes 70mW at 1.8V power-supply.