A 2.8 Gb/s, 32-state, radix-4 Viterbi decoder add-compare-select unit

A 0.13 /spl mu/m CMOS add-compare-select unit (ACSU) is presented allowing for a maximum data rate of 2.8 Gb/s. A modified bit-level pipelining scheme combined with a new state metric representation has been implemented using single-rail DOMINO logic and static CMOS gates. The adaptation of architecture and circuit technique results in a compact energy-efficient design. The 0.5mm/sup 2/ chip consumes 970mW at 2 Gb/s (VDD = 1.2 V) and 2.2 W at 2.8 Gb/s (VDD = 1.5 V).