Improving symbolic analysis in CMOS analog integrated circuits

A symbolic method to improve the computation of simple symbolic expressions (SEs), which represent the dominant behavior of a CMOS analog IC, is presented. It is demonstrated that the complexity in manipulating ESs, being minimized by modelling the behavior of the MOSFET using nullors, at different levels of abstraction. In this manner, to improve traditional symbolic methods, the formulation of a compacted system of equations (CSEss) is computed herein by selecting the simplest model for the MOSFET, and by manipulating the interconnection-relationships of the circuit. The proposed method sets the guidelines to select the correct model, which minimizes computer-tasks by considering the bias and frequency operating conditions of every MOSFET.